Implementation of High Resolution and Power Efficient ∑∆ Adc Using Pipeline Configuration Technique
نویسنده
چکیده
A high resolution analog to digital converter (ADC) is presented and it’s dedicated to neural recording systems. By employing two continuous time incremental sigmadelta(I∑∆) ADC in a pipeline configuration, without sacrificing the conversion rate the proposed ADC can obtain high resolution. This two-step architecture is furthermore power efficient, as the resolution need for the incremental ADC in each and every step is significantly relaxed. In order to upgrade the power efficiency, a dynamic summing comparator and class AB output stage are used to implement the sigma delta modulators. The proposed circuit achieved a gain bandwidth of 50MHz, supply voltage of 3V/1.8V and the noise voltage is reduced by 0.000002V. Keywords— continuous time, two step ADC, pipeline configuration, incremental sigma-delta ADC
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